Paper Infomation
Network on Chip-based Fault Tolerant Routing Algorithm and Its Implementation
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Author: Shuyan Jiang, Shanshan Jiang, Peng Liu, Yue Liu, He Cheng
Abstract: In this paper, a new fault-tolerant routing algorithm is presented in order to effectively improve the fault-tolerant performance of NoC. Based on a classical XY dimension routing algorithm, this design realizes a fault-tolerant routing algorithm of a single routing error by increasing its adaptability, and maintains the advantages of the XY routing algorithm, such as simpleness, hardware overhead, and scalability. Then a 3*3 structure of 2D-mesh Noc is simulated in ISE Design Suit 14.1 platform. Experiment results show that the proposed fault-tolerant routing algorithm proposed can complete the functions of routing data forwarding and tolerance of a single fault on NoC.
Keywords: Network on Chip; Fault-tolerant; Routing Algorithm; Topology
References:
[1] Lai MingChe, Gao Lei, Xiao Nong, Wang Zhi Ying. An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network [J]. Sicience China Information Sciences, 2013, vol.56, pp.1-20
[2] Meyer, Q., Keinert, B., Sußner, G., Stamminger, M. Data-Parallel Decompression of Triangle Mesh Topology [J]. Computer Graphics Forum, 2012, vol. 31, pp. 266-278
[3] Edward Birrane. Analysis of the contact graph routing algorithm: Bounding interplanetary paths [J]. Acta Astronautica, 2012, vol 75, pp.108-119
[4] Yuanwei Jing, Yan Wang. Geographic Routing Algorithm with Location Errors [J]. IEICE Transactions on Information and Systems,2012, vol.E95-D, pp.3092-3096
[5] Chun-Ying Liu. Adaptive search protocol based on optimized ant colony algorithm in peer-to-peer network [J]. Journal of Networks, 2013, vol.8, pp. 843-850
[6] Lotfi-Kamran, P. , Rahmani, A.,M. Daneshtalab, M., Afzali-Kusha, A.. EDXY-A low cost congestion-aware routing algorithm for network-on-chips. Journal of Systems Architecture, 2010, vol.56, pp. 256-264
[7] L. Benini, G. De Micheli. Networks on Chip: A new SoC Paradigm [J]. IEEE Computer Magazine, 2002, 35(1): 70-78
[8] Mojtaba Valinataj, Pasi Liljeberg, Juha Plosila. A Fault-Tolerant and Hierarchical Routing Algorithm for Noc Architectures. NORCHIP, 2011:1-6
[9] L. Benini, G. de Micheli. Networks on chips: a new SoC paradigm. Computer. january. 2002: 70-78
[10] Mediratta, S.D. Draper.J. Characterization of a Fault-tolerant NoC Router. Circuits and Systems, 2007: 381-38